Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories

TL;DR

This paper explores the design space of dense FeFET-based embedded non-volatile memories, optimizing for performance, energy, and accuracy in data-intensive applications, achieving high density and low latency without accuracy loss.

Contribution

It provides a comprehensive cross-stack design exploration of FeFET memory architectures, balancing device, circuit, and system considerations for practical, high-density, low-latency memory solutions.

Findings

Achieved over 8MB/mm^2 density for storing DNN weights and social network graphs.

Realized sub-2ns read latency without compromising application accuracy.

Optimized memory design parameters for energy efficiency and reliability.

Abstract

The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm^2 and sub-2ns read access latency without loss in application accuracy.