Content Addressable Parallel Processors on a FPGA

TL;DR

This paper presents the first FPGA implementation of a Content Addressable Parallel Processor that supports parallel write and output combining, enabling advanced parallel processing capabilities accessible via USB/UART.

Contribution

It introduces a novel FPGA-based implementation of Caxton Foster's parallel processing vision, including parallel write and output combining features.

Findings

Successful FPGA implementation of CAPP with parallel write

Demonstrated USB/UART access with a Python driver

First known FPGA realization of Foster's parallel processing concepts

Abstract

In this short article, we report on the implementation of a Content Addressable Parallel Processor using a FPGA. While Content addressable memories have been implemented in FPGAs, to our knowledge this is the first implementation in FPGA of Caxton C. Foster's vision of parallel processing, particularly the notions of parallel write as well as the combining of output values, which are usually missing in more typical CAM implementations, such as the ones designed for network routing. The resulting CAPP is made accessible to a host computer over a USB/UART interface, using a straightforward serial protocol that is demonstrated using a Python-based driver.