Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection
Karthik Ganesan, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan, Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark, Barrett, Subhasish Mitra

TL;DR
This paper introduces an enhanced symbolic quick error detection method for pre-silicon verification of processor cores, enabling early bug detection, including long-trace bugs and hardware Trojans, by extending BMC with symbolic starting states and constraints.
Contribution
The paper presents a novel extension of SQED with symbolic starting states and constraints, improving bug detection capabilities in processor verification.
Findings
Successfully detected previously unknown bugs in open-source RISC-V cores.
Outperformed existing methods in detecting long-trace bugs.
Effectively identified hardware Trojans in processor designs.
Abstract
We present a novel approach to pre-silicon verification of processor designs. The purpose of pre-silicon verification is to find logic bugs in a design at an early stage and thus avoid time- and cost-intensive post-silicon debugging. Our approach relies on symbolic quick error detection (Symbolic QED, or SQED). SQED is targeted at finding logic bugs in a symbolic representation of a design by combining bounded model checking (BMC) with QED tests. QED tests are powerful in generating short sequences of instructions (traces) that trigger bugs. We extend an existing SQED approach with symbolic starting states. This way, we enable the BMC tool to select starting states arbitrarily when generating a trace. To avoid false positives, (e.g., traces starting in unreachable states that may not be-have in accordance with the processor instruction-set architecture), we define constraints to…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis · VLSI and Analog Circuit Testing
