Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks
Yusuke Sakemi, Takashi Morie, Takeo Hosomi, Kazuyuki Aihara

TL;DR
This paper investigates how VLSI circuit constraints like time discretization and weight quantization affect the performance of temporal-coding multilayer spiking neural networks and proposes an optimal mapping approach.
Contribution
It provides a detailed analysis of circuit-induced non-idealities on SNN performance and introduces an optimal method for mapping SNN models to analog VLSI circuits.
Findings
Time discretization impacts SNN accuracy.
Weight quantization affects spike timing precision.
Proposed mapping improves robustness to circuit constraints.
Abstract
The spiking neural network (SNN) has been attracting considerable attention not only as a mathematical model for the brain, but also as an energy-efficient information processing model for real-world applications. In particular, SNNs based on temporal coding are expected to be much more efficient than those based on rate coding, because the former requires substantially fewer spikes to carry out tasks. As SNNs are continuous-state and continuous-time models, it is favorable to implement them with analog VLSI circuits. However, the construction of the entire system with continuous-time analog circuits would be infeasible when the system size is very large. Therefore, mixed-signal circuits must be employed, and the time discretization and quantization of the synaptic weights are necessary. Moreover, the analog VLSI implementation of SNNs exhibits non-idealities, such as the effects of…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Neural dynamics and brain function · Neuroscience and Neural Engineering
