Quantized Neural Networks via {-1, +1} Encoding Decomposition and Acceleration

TL;DR

This paper introduces a novel {-1,+1} encoding scheme for quantized neural networks that decomposes them into binary networks, enabling efficient implementation with bitwise operations for model compression and acceleration, especially suitable for resource-constrained devices.

Contribution

The paper presents a new encoding scheme that allows flexible precision and efficient hardware implementation of quantized neural networks, improving their applicability on embedded systems.

Findings

Achieves near high-bit performance with low-bit encoding on ImageNet.

Enables efficient FPGA and ASIC deployment with bitwise operations.

Provides flexible precision control for different hardware constraints.

Abstract

The training of deep neural networks (DNNs) always requires intensive resources for both computation and data storage. Thus, DNNs cannot be efficiently applied to mobile phones and embedded devices, which severely limits their applicability in industrial applications. To address this issue, we propose a novel encoding scheme using {-1, +1} to decompose quantized neural networks (QNNs) into multi-branch binary networks, which can be efficiently implemented by bitwise operations (i.e., xnor and bitcount) to achieve model compression, computational acceleration, and resource saving. By using our method, users can achieve different encoding precisions arbitrarily according to their requirements and hardware resources. The proposed mechanism is highly suitable for the use of FPGA and ASIC in terms of data storage and computation, which provides a feasible idea for smart chips. We validate the effectiveness of our method on large-scale image classification (e.g., ImageNet), object detection, and semantic segmentation tasks. In particular, our method with low-bit encoding can still achieve almost the same performance as its high-bit counterparts.