Spatiotemporal Pattern Recognition in Single Mixed-Signal VLSI Neurons with Heterogeneous Dynamic Synapses

TL;DR

This paper demonstrates a low-power, hardware-efficient spatiotemporal pattern recognition method using mixed-signal neuromorphic processors with heterogenous synapses, inspired by brain circuitry, for improved spike-timing processing.

Contribution

It introduces a novel thalamocortically inspired neural network utilizing disynaptic lateral connections without delay mechanisms, optimized for neuromorphic hardware.

Findings

Disynaptic lateral connections reduce energy consumption by an order of magnitude.

Receptive fields of coincidence-detection neurons successfully mapped in hardware.

Neurons tuned to specific spatiotemporal features via synaptic reprogramming.

Abstract

Mixed-signal neuromorphic processors with brain-like organization and device physics offer an ultra-low-power alternative to the unsustainable developments of conventional deep learning and computing. However, realizing the potential of such neuromorphic hardware requires efficient use of its heterogeneous, analog neurosynaptic circuitry with neurocomputational methods for sparse, spike-timing-based encoding and processing. Here, we investigate the use of balanced excitatory-inhibitory disynaptic lateral connections as a resource-efficient mechanism for implementing a thalamocortically inspired Spatiotemporal Correlator (STC) neural network without using dedicated delay mechanisms. We present hardware-in-the-loop experiments with a DYNAP-SE neuromorphic processor, in which receptive fields of heterogeneous coincidence-detection neurons in an STC network with four lateral afferent connections per column were mapped by random input-sampling. Furthermore, we demonstrate how such a neuron was tuned to detect a particular spatiotemporal feature by discrete address-reprogramming of the analog synaptic circuits. The energy dissipation of the disynaptic connections is one order of magnitude lower per lateral connection (0.65 nJ vs 9.6 nJ per spike) than in the former delay-based hardware implementation of the STC.