Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices

TL;DR

This paper introduces a multiplierless kernel machine framework optimized for FPGA edge devices, using piecewise linear approximation and margin propagation to achieve energy-efficient inference and training.

Contribution

The paper presents a novel FPGA-optimized multiplierless kernel machine framework utilizing MP-based PWL approximation for energy-efficient edge computing.

Findings

Reduces FPGA energy consumption to 13.4 pJ

Eliminates DSP units, reducing resource usage

Achieves superior power, performance, and area metrics

Abstract

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a Field Programmable Gate Array (FPGA) platform. Our FPGA implementation eliminates the need for DSP units and reduces the number of LUTs. By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from the MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9k LUTs and FFs each for a 256 x 32 sized kernel making it superior in terms of power, performance, and area compared to other comparable implementations.