Reuse Distance-based Copy-backs of Clean Cache Lines to Lower-level Caches
Rui Wang, Chundong Wang, Chongnan Ye

TL;DR
This paper proposes a selective reuse distance-based copy-back policy for clean cache lines in multi-level caches, improving performance in exclusive and non-inclusive cache architectures with STT-MRAM.
Contribution
It introduces a novel reuse distance-based approach to selectively copy back clean cache lines, optimizing cache utilization and performance.
Findings
Up to 12.8% higher IPC throughput with the proposed method.
Effective in architectures with non-volatile LLC (STT-MRAM).
Outperforms traditional LRU policy in experimental evaluations.
Abstract
Cache plays a critical role in reducing the performance gap between CPU and main memory. A modern multi-core CPU generally employs a multi-level hierarchy of caches, through which the most recently and frequently used data are maintained in each core's local private caches while all cores share the last-level cache (LLC). For inclusive caches, clean cache lines replaced in higher-level caches are not necessarily copied back to lower levels, as the inclusiveness implies their existences in lower levels. For exclusive and non-inclusive caches that are widely utilized by Intel, AMD, and ARM today, either indiscriminately copying back all or none of replaced clean cache lines to lower levels raises no violation to exclusiveness and non-inclusiveness definitions. We have conducted a quantitative study and found that, copying back all or none of clean cache lines to lower-level cache of…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Data Storage Technologies · Distributed systems and fault tolerance
