Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

TL;DR

This paper introduces an approximate MRAM framework that leverages error resilience to significantly improve performance and reduce power consumption, especially in error-tolerant applications like image processing.

Contribution

It presents a systematic methodology to construct an approximate MRAM system using COTS chips by exploiting intrinsic error behaviors for performance and power gains.

Findings

Achieved up to 66% reduction in write current.

Demonstrated significant performance improvements.

Maintained output quality in error-tolerant applications.

Abstract

Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results and error-resilient image application reveal that the proposed AC framework provides a significant performance improvement and demonstrates a maximum reduction in MRAM write current of ~66% on average with negligible or no loss in output quality.