The Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors

TL;DR

This paper presents a charge balance model for ferroelectric FETs, revealing that interface layers critically influence memory performance and explaining discrepancies between capacitor and transistor behaviors.

Contribution

A comprehensive charge balance model for Fe-FETs is developed, highlighting the importance of interface layers in determining device memory characteristics.

Findings

FE/DE interface and DE layer are critical for memory performance

The model explains discrepancies between FE capacitors and Fe-FETs

Experimental results align with the proposed charge balance framework

Abstract

Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as gate insulator are being extensively explored as a promising device candidate for three-dimensional (3D) NAND memory application. FE HfO2 exhibits long retention over 10 years, high endurance over 1012 cycles, high speed with sub-ns polarization switching, and high remnant polarization of 10-30 {\mu}C/cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with M/FE/DE/S (Metal/Ferroelectric/Dielectric/Semiconductor) gate stack is studied. It is found that the FE/DE interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood.