A Flexible FPGA-Based ISA Configurable SoC platform
Shih-Yi Yuan, Bo-Yu Zhu

TL;DR
This paper presents a flexible FPGA-based platform capable of generating customizable hardware/software configurations based on various instruction set architectures, enabling resource-efficient, purpose-specific microcontrollers with adaptable features.
Contribution
The platform allows dynamic generation of ISAs, MCUs, and assemblers on FPGA, demonstrating flexibility and resource reduction for tailored hardware solutions.
Findings
Effective resource reduction on FPGA
Supports multiple custom ISAs and MCUs
Successfully controls hardware IPs and multi-task OS
Abstract
We proposes a platform which can generate hardware/software description based on flexible in-struction set architectures (ISAs). The platform takes advantage of the flexibility of field pro-grammable gate array (FPGA) to design many micro control units (MCUs) based on different ISAs. The platform can generate many ISAs, MCUs, and Assemblers according to a pre-defined ISA and user applications. Although the MCU performance is not optimized, the FPGA shows a great potential on resource reduction and enough performance at very low system clock rate. The flexible ISA has shown great importance for the design targeted to specific purpose. We also show a case study of the proposed flexible ISA-based FPGA-MCU. It can control many specifi-cally designed hardware IPs and a customized multi-task OS with tasks. Not only the case works correctly, but also the proposed FPGA-MCU of the case is…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsEmbedded Systems Design Techniques · Parallel Computing and Optimization Techniques · Interconnection Networks and Systems
