Prefetcher-based DRAM Architecture
Saurabh Jaiswal, Shailendra Kumar Gupta, Soumya Soubhagya Dandapat

TL;DR
This paper proposes integrating data prediction techniques into DRAM architectures like TL-DRAM and CROW to prefetch data into faster memory sections, aiming to reduce memory access latency and improve overall system performance.
Contribution
It introduces a novel approach of applying data prediction at the DRAM architecture level, specifically within TL-DRAM and CROW, to enhance data transfer efficiency.
Findings
Potential reduction in memory access latency
Improved data transfer efficiency in DRAM architectures
Enhanced overall system performance
Abstract
Advancement in Processor technology has made it easy to handle data-intensive workloads, but limiting main memory advances has created performance bottlenecks. In DRAM, there have been improvements in DRAM access latency as well as reduction in cost-per-bit with the increase in cell density. But still DRAM data transfer rate lags behind the processing speed of the current generation processors. As Memory advancements based on hardware have been progressing at a slower pace, to cope up with High-end Processors, Architectural level advancements such as Prediction techniques, Replacement policies, etc are the major subject. In the recent field of research, Data prediction is a sought out topic as correct prediction can boost performance by decreasing the amount of excess memory access by predicting data beforehand using data access trends and behaviors. Though prediction techniques have…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Data Storage Technologies · Low-power high-performance VLSI design
