ATLAS ITk Pixel Detector Overview

TL;DR

This paper provides an overview of the design, development, and current status of the ATLAS ITk Pixel Detector upgrade for the High Luminosity LHC, highlighting technological innovations and prototyping efforts.

Contribution

It presents the detailed layout, technological choices, and progress in developing the all-silicon Inner Tracker for the ATLAS experiment upgrade.

Findings

Successful development of hybrid detector modules with novel ASICs

Implementation of serial powering to reduce material budget

Progress in large-scale prototyping of the pixel detector system

Abstract

For the High Luminosity upgrade of the Large Hadron Collider the current ATLAS Inner Detector will be replaced by an all-silicon Inner Tracker. The pixel detector will consist of five barrel layers and a number of rings, resulting in about 13 m^2 of instrumented area. Due to the huge non-ionising fluence (1e16 neq/cm^2) and ionising dose (5 MGy), the two innermost layers, instrumented with 3D pixel sensors and 100 um thin planar sensors, will be replaced after about five years of operation. Each pixel layer comprises hybrid detector modules that will be read out by novel ASICs, implemented in 65 nm CMOS technology, with a bandwidth of up to 5 Gbit/s. Data will be transmitted optically to the off-detector readout system. To save material in the servicing cables, serial powering is employed for the supply voltage of the readout ASICs. Large scale prototyping programmes are being carried out by all subsystems. This paper will give an overview of the layout and current status of the development of the ITk Pixel Detector.