Optimizing the Use of Behavioral Locking for High-Level Synthesis

TL;DR

This paper introduces a meta-framework for optimizing behavioral logic locking during high-level synthesis, enhancing security while reducing overhead and resource usage in hardware design.

Contribution

It presents a novel, application-independent method to automatically optimize security metrics in behavioral locking during HLS, compatible with existing industrial tools.

Findings

Always finds valid security-optimized solutions

Reduces locking bits by over 90%

Achieves higher security with similar overheads

Abstract

The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a meta-framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip's specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our meta-framework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric.