A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream

TL;DR

This paper presents a hardware implementation of a connected component labelling module capable of processing 4K UltraHD video streams at 60 fps with 4 pixels per clock, supporting real-time video analysis without simplifications.

Contribution

The design introduces a novel labelling method and a mechanism to handle multi-pixel groups, enabling full support for 4 ppc and real-time 4K video processing in hardware.

Findings

Successfully verified in simulation and hardware

Achieves real-time processing of 4K/UltraHD at 60 fps

Supports 4 pixels per clock without simplifications

Abstract

This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the "full", i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.