High performance and energy efficient inference for deep learning on ARM processors

TL;DR

This paper presents an optimized deep learning inference framework for ARM processors that improves throughput and energy efficiency by leveraging thread-level parallelism, micro-kernels, and cache tuning, demonstrated on ResNet50.

Contribution

It introduces a highly optimized inference engine for ARM processors with novel micro-kernels and cache configurations, outperforming TFLite and approaching ArmNN performance.

Findings

Superior inference throughput compared to TFLite.

Energy-efficient inference on ARM processors.

Competitive performance with ArmNN.

Abstract

We evolve PyDTNN, a framework for distributed parallel training of Deep Neural Networks (DNNs), into an efficient inference tool for convolutional neural networks. Our optimization process on multicore ARM processors involves several high-level transformations of the original framework, such as the development and integration of Cython routines to exploit thread-level parallelism; the design and development of micro-kernels for the matrix multiplication, vectorized with ARMs NEON intrinsics, that can accommodate layer fusion; and the appropriate selection of several cache configuration parameters tailored to the memory hierarchy of the target ARM processors. Our experiments evaluate both inference throughput (measured in processed images/s) and inference latency (i.e., time-to-response) as well as energy consumption per image when varying the level of thread parallelism and the processor power modes. The experiments with the new inference engine are reported for the ResNet50 v1.5 model on the ImageNet dataset from the MLPerf suite using the ARM v8.2 cores in the NVIDIA Jetson AGX Xavier board. These results show superior performance compared with the well-spread TFLite from Google and slightly inferior results when compared with ArmNN, the native library from ARM for DNN inference.