TL;DR
This paper introduces a non-blocking, high-resolution digital delay line using FPGA logic primitives, achieving adjustable delays from 23 ns to 1635 ns with 10 ps resolution, minimal dead time, and manageable jitter for photonic network applications.
Contribution
The authors present a novel asynchronous circuit design for a programmable delay line with optimized resolution, delay range, and dead time, addressing key issues like thermal stability and pulse spreading.
Findings
Delay range from 23 ns to 1635 ns with 10 ps resolution
Timing jitter ranges from 7 ps to 165 ps, increasing linearly with delay
Dead time achieved between 4 ns and 22.5 ns
Abstract
We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23 ns up to 1635 ns with a resolution of 10 ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps/K per a logic primitive. We measured the timing jitter of the delay to be in the range of 7 ps - 165 ps, linearly increasing over…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Code & Models
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
