TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators

TL;DR

TRIM is a comprehensive model that enables early-stage exploration of hardware design options for deep neural network accelerators, optimizing for both inference and training efficiency.

Contribution

It introduces a novel infrastructure that evaluates entire network architectures considering various hardware configurations, guiding optimal design choices.

Findings

Validated with FPGA and ASIC implementations.

Effectively guides hardware architecture design.

Supports exploration of dataflow and hardware options.

Abstract

There is increasing demand for specialized hardware for training deep neural networks, both in edge/IoT environments and in high-performance computing systems. The design space of such hardware is very large due to the wide range of processing architectures, deep neural network configurations, and dataflow options. This makes developing deep neural network processors quite complex, especially for training. We present TRIM, an infrastructure to help hardware architects explore the design space of deep neural network accelerators for both inference and training in the early design stages. The model evaluates at the whole network level, considering both inter-layer and intra-layer activities. Given applications, essential hardware specifications, and a design goal, TRIM can quickly explore different hardware design options, select the optimal dataflow and guide new hardware architecture design. We validated TRIM with FPGA-based implementation of deep neural network accelerators and ASIC-based architectures. We also show how to use TRIM to explore the design space through several case studies. TRIM is a powerful tool to help architects evaluate different hardware choices to develop efficient inference and training architecture design.