IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks
Amogh Agrawal, Mustafa Ali, Minsuk Koo, Nitin Rathi, Akhilesh Jaiswal,, Kaushik Roy

TL;DR
This paper introduces a 65nm compute-in-memory macro for spiking neural networks that fuses weight and membrane potential memory, significantly reducing energy consumption and enabling efficient sequential learning.
Contribution
It presents a novel 10T-SRAM CIM macro with fused weight and membrane potential memory, exploiting sparsity for energy efficiency in SNN inference.
Findings
Achieves 97.4% reduction in energy-delay-product at 85% sparsity.
Fabricated in 65nm CMOS with 0.99 TOPS/W energy efficiency.
Performs sentiment classification with near-LSTM accuracy, using fewer parameters.
Abstract
The inherent dynamics of the neuron membrane potential in Spiking Neural Networks (SNNs) allows processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly-sparse spike-based computations in such spatio-temporal data can be leveraged for energy-efficiency. However, the membrane potential incurs additional memory access bottlenecks in current SNN hardware. To that effect, we propose a 10T-SRAM compute-in-memory (CIM) macro, specifically designed for state-of-the-art SNN inference. It consists of a fused weight (WMEM) and membrane potential (VMEM) memory and inherently exploits sparsity in input spikes leading to 97.4% reduction in energy-delay-product (EDP) at 85% sparsity (typical of SNNs considered in this work) compared to the case of no sparsity. We propose staggered data mapping and reconfigurable peripherals for handling different…
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