Hardware Synthesis of State-Space Equations; Application to FPGA Implementation of Shallow and Deep Neural Networks
Amir-Hossein Kiamarzi, Pezhman Torabi, Reza Sameni

TL;DR
This paper introduces a systematic approach for implementing neural networks using state-space models in RTL, facilitating efficient FPGA deployment and optimization, especially for recurrent networks like LSTMs.
Contribution
It presents a novel design flow based on state-space models for systematic, automated FPGA implementation of neural networks, including a software tool for RTL code generation.
Findings
Effective implementation of NNs using state-space models.
Automated RTL code generation for arbitrary NN sizes.
Application to recurrent neural networks like LSTM.
Abstract
Nowadays, shallow and deep Neural Networks (NNs) have vast applications including biomedical engineering, image processing, computer vision, and speech recognition. Many researchers have developed hardware accelerators including field-programmable gate arrays (FPGAs) for implementing high-performance and energy efficient NNs. Apparently, the hardware architecture design process is specific and time-consuming for each NN. Therefore, a systematic way to design, implement and optimize NNs is highly demanded. The paper presents a systematic approach to implement state-space models in register transfer level (RTL), with special interest for NN implementation. The proposed design flow is based on the iterative nature of state-space models and the analogy between state-space formulations and finite-state machines. The method can be used in linear/nonlinear and time-varying/time-invariant…
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Taxonomy
TopicsNeural Networks and Applications · Numerical Methods and Algorithms · Fault Detection and Control Systems
