High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND

TL;DR

This paper presents the first hardware architecture for ORBGRAND, achieving high throughput and flexibility for decoding linear error-correcting codes, significantly outperforming existing decoders like Fast-DSCF in speed.

Contribution

It introduces a novel VLSI architecture for ORBGRAND, enabling high-throughput decoding of any linear code with comparable performance to state-of-the-art methods.

Findings

Achieves up to 42.5 Gbps throughput for a 128-bit code at 10 dB SNR.

Can decode any linear code within length and rate constraints.

Outperforms Fast-DSCF by 49 times in throughput for a 5G polar code.

Abstract

Guessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND technique by generating error patterns in a specific order. Moreover, their simplicity at the algorithm level renders GRAND family a desirable candidate for applications that demand very high throughput. This work reports the first-ever hardware architecture for ORBGRAND, which achieves an average throughput of up to $42.5$ Gbps for a code length of $128$ at an SNR of $10$ dB. Moreover, the proposed hardware can be used to decode any code provided the length and rate constraints. Compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar $(128,105)$ code, the proposed VLSI implementation has $49\times$ more average throughput while maintaining similar decoding performance.