Fault-Resilient PCIe Bus with Real-time Error Detection and Correction

TL;DR

This paper introduces a new PCIe interface IP that enables real-time error detection and correction, enhancing fault resilience for FPGA-based systems interfacing with host PCs.

Contribution

It presents a novel FPGA IP design capable of on-the-fly PCIe error detection and correction, improving system reliability.

Findings

Effective real-time error detection and correction demonstrated

Enhanced fault resilience in PCIe communication

Applicable to FPGA-based host interface systems

Abstract

This paper presents a novel IP design for real-time fault/error detection and recovery on a peripheral component interconnect express (PCIe) which interfaces a host system (here a PC) to a slave design including processing system and memory transaction implemented on a Zynq Ultrascale Xilinx Kintex FPGA board (KCU105). The proposed IP design is capable of detection and correction of different types of PCIe errors on-the-fly