On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains

TL;DR

This paper introduces an approximate sequential multiplier that adjusts accuracy and latency by segmenting carry chains, offering resource-efficient multiplication suitable for FPGA and ASIC implementations.

Contribution

It proposes a novel carry chain segmentation technique for configurable accuracy in sequential multipliers, with comprehensive implementation and error analysis.

Findings

Reduced latency compared to accurate multipliers

Area savings over combinatorial approaches

Effective accuracy-latency trade-offs demonstrated

Abstract

In this paper, we present a multiplier based on a sequence of approximated accumulations. According to a given splitting point of the carry chains, the technique herein introduced allows varying the quality of the accumulations and, consequently, the overall product. Our approximate multiplier trades-off accuracy for a reduced latency (with respect to an accurate sequential multiplier) and exploits the inherent area savings of sequential over combinatorial approaches. We implemented multiple versions with different bit-width and accuracy configurations, targeting an FPGA and a 45nm ASIC to estimate resources, power consumption, and latency. We also present two error analyses of the proposed design based on closed-form analysis and simulations.