Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS

TL;DR

This paper introduces a skew-oblivious data routing architecture for FPGAs that dynamically balances workload among processing elements, improving performance and resource efficiency for data-intensive applications with skewed data distributions.

Contribution

The paper presents a novel skew-oblivious data routing architecture integrated into the Ditto framework, enabling robust and efficient FPGA implementations for skewed data workloads.

Findings

Outperforms state-of-the-art designs in throughput.

Reduces BRAM usage compared to existing methods.

Demonstrates robustness on five data-intensive applications.

Abstract

FPGAs have become emerging computing infrastructures for accelerating applications in datacenters. Meanwhile, high-level synthesis (HLS) tools have been proposed to ease the programming of FPGAs. Even with HLS, irregular data-intensive applications require explicit optimizations, among which multiple processing elements (PEs) with each owning a private BRAM-based buffer are usually adopted to process multiple data per cycle. Data routing, which dynamically dispatches multiple data to designated PEs, avoids data replication in buffers compared to statically assigning data to PEs, hence saving BRAM usage. However, the workload imbalance among PEs vastly diminishes performance when processing skew datasets. In this paper, we propose a skew-oblivious data routing architecture that allocates secondary PEs and schedules them to share the workload of the overloaded PEs at run-time. In addition, we integrate the proposed architecture into a framework called Ditto to minimize the development efforts for applications that require skew handling. We evaluate Ditto on five commonly used applications: histogram building, data partitioning, pagerank, heavy hitter detection and hyperloglog. The results demonstrate that the generated implementations are robust to skew datasets and outperform the stateof-the-art designs in both throughput and BRAM usage efficiency.