Efficiency-driven Hardware Optimization for Adversarially Robust Neural Networks
Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda

TL;DR
This paper explores hardware-based strategies, including hybrid SRAM memories and memristive crossbars, to enhance adversarial robustness of neural networks by leveraging hardware-induced noise and errors.
Contribution
It introduces novel hardware optimization techniques that induce beneficial noise and errors, improving DNN robustness against adversarial attacks.
Findings
Hybrid 6T-8T memories bound noise within limits, reducing adversarial perturbations.
Analog memristive crossbars' non-idealities confer robustness to DNNs.
Hardware-induced errors can be exploited to improve neural network security.
Abstract
With a growing need to enable intelligence in embedded devices in the Internet of Things (IoT) era, secure hardware implementation of Deep Neural Networks (DNNs) has become imperative. We will focus on how to address adversarial robustness for DNNs through efficiency-driven hardware optimizations. Since memory (specifically, dot-product operations) is a key energy-spending component for DNNs, hardware approaches in the past have focused on optimizing the memory. One such approach is approximate digital CMOS memories with hybrid 6T-8T SRAM cells that enable supply voltage (Vdd) scaling yielding low-power operation, without significantly affecting the performance due to read/write failures incurred in the 6T cells. In this paper, we show how the bit-errors in the 6T cells of hybrid 6T-8T memories minimize the adversarial perturbations in a DNN. Essentially, we find that for different…
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