Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

TL;DR

This paper investigates how different synaptic waveforms and timescales in Liquid State Machines affect speech classification accuracy and hardware efficiency, finding that simpler synapses can achieve comparable results with significant hardware savings.

Contribution

It demonstrates that 0th order synapses perform as well as complex 2nd order synapses in speech classification, enabling more hardware-efficient neuromorphic implementations.

Findings

0th order synapses match 2nd order accuracy in speech recognition

Optimal reservoir activity correlates with classification performance

Significant area and power savings achieved with simpler synaptic circuits

Abstract

Liquid State Machines are brain inspired spiking neural networks (SNNs) with random reservoir connectivity and bio-mimetic neuronal and synaptic models. Reservoir computing networks are proposed as an alternative to deep neural networks to solve temporal classification problems. Previous studies suggest 2nd order (double exponential) synaptic waveform to be crucial for achieving high accuracy for TI-46 spoken digits recognition. The proposal of long-time range (ms) bio-mimetic synaptic waveforms is a challenge to compact and power efficient neuromorphic hardware. In this work, we analyze the role of synaptic orders namely: {\delta} (high output for single time step), 0th (rectangular with a finite pulse width), 1st (exponential fall) and 2nd order (exponential rise and fall) and synaptic timescales on the reservoir output response and on the TI-46 spoken digits classification accuracy under a more comprehensive parameter sweep. We find the optimal operating point to be correlated to an optimal range of spiking activity in the reservoir. Further, the proposed 0th order synapses perform at par with the biologically plausible 2nd order synapses. This is substantial relaxation for circuit designers as synapses are the most abundant components in an in-memory implementation for SNNs. The circuit benefits for both analog and mixed-signal realizations of 0th order synapse are highlighted demonstrating 2-3 orders of savings in area and power consumptions by eliminating Op-Amps and Digital to Analog Converter circuits. This has major implications on a complete neural network implementation with focus on peripheral limitations and algorithmic simplifications to overcome them.