Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis

TL;DR

This paper introduces an automated method for designing specialized CGRA processing elements by mining frequent subgraphs from application sets, resulting in architectures that significantly improve energy efficiency and reduce area.

Contribution

It presents a novel approach using frequent subgraph analysis to automatically generate application-specific CGRA processing elements.

Findings

Specialized PEs are up to 10.5x more energy efficient.

Generated PEs consume 9.1x less area.

Method improves design efficiency for image processing and machine learning domains.

Abstract

The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. This paper presents an automated approach for generating specialized PE architectures for an application or an application domain. Frequent subgraphs mined from a set of applications are merged to form a PE architecture specialized to that application domain. For the image processing and machine learning domains, we generate specialized PEs that are up to 10.5x more energy efficient and consume 9.1x less area than a baseline PE.