Channel Models and Coding Solutions for 1S1R Crossbar Resistive Memory with High Line Resistance
Zehui Chen, Lara Dolecek

TL;DR
This paper models the effects of line resistance and variability in 1S1R crossbar resistive memory, proposing channel models and coding schemes to improve reliability and reduce error rates in scaled memory devices.
Contribution
It introduces BAC channel models considering line resistance and variability, and proposes coding solutions including interleaved BCH codes and location-dependent coding for enhanced reliability.
Findings
Models show non-uniform bit-error rates across arrays.
Optimized read threshold reduces raw bit-error rate.
Coding schemes significantly lower undetected error rates.
Abstract
Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure is attractive for nonvolatile, high-density, and low-latency storage-class memory applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. This paper presents write/read communication channels while considering the line resistance and device variabilities by statistically relating the degraded write/read margins and the channel parameters. Binary asymmetric channel (BAC) models are proposed for the write/read operations. Simulations based on these models suggest that the bit-error rate of devices are highly non-uniform across the memory array. These models provide quantitative tools for evaluating the trade-offs between memory reliability and design parameters, such as array size, technology nodes, and aspect…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices
