New design approach of Front-End Electronics for high-accuracy time measurement systems used in particle detection

TL;DR

This paper presents a comprehensive design methodology for optimizing input impedance and bandwidth in front-end electronics to enhance timing accuracy in particle detection systems, supported by simulations and modeling.

Contribution

It introduces a new mathematical model for estimating timing jitter considering parasitic inductances and demonstrates its effectiveness through simulations and a CMOS-based amplifier design.

Findings

Optimal Rin and BW significantly improve timing accuracy.

The new jitter estimation model aligns well with simulation results.

Design approach reduces timing jitter in high-precision particle detection.

Abstract

This paper discusses a detailed design approach to determine the optimal input impedance (Rin) and bandwidth (BW) for current preamplifiers in Front End Electronics (FEE) of high-accuracy time measurement systems used in particle detection. Our study shows the effect of the input impedance Rin including the parasitic interconnection inductances of bonding wires between the detector and the FEE. We explain also the development of a new mathematical model for the estimation of the timing jitter of the current preamplifier in the case of using a low capacitor detector (Cd) as diamond. Different simulations based on developed MATLAB Simulink behavioral models are done in addition to an electric simulation of a transimpedance amplifier (TIA) designed in a 130 nm 1P8M CMOS technology which demonstrates the accuracy of the design approach and the timing jitter estimation model.