CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses

TL;DR

CodeAPeel is a layered simulation tool for computer architecture education, supporting instruction processing, register behavior, and vectorization in a generic RISC ISA, enhancing teaching of core concepts.

Contribution

It introduces a versatile, layered simulation technology that models both scalar and vector instructions in a generic RISC architecture for educational purposes.

Findings

Supports simulation of fetch-decode-execute cycle

Visualizes CPU registers, memory, and graphics

Enables dual-mode scalar and vector processing

Abstract

This paper introduces a versatile, multi-layered technology to help support teaching and learning core computer architecture concepts. This technology, called CodeAPeel is already implemented in one particular form to describe instruction processing in compiler, assembly, and machine layers of a generic instruction set architecture by a comprehensive simulation of its fetch-decode-execute cycle as well as animation of the behavior of its CPU registers, RAM, VRAM, STACK memories, various control registers, and graphics screen. Unlike most educational CPU simulators that simulate a real processor such as MIPS or RISC-V, CodeAPeel is designed and implemented as a generic RISC instruction set architecture simulator with both scalar and vector instructions to provide a dual-mode processor simulator as described by Flynn's classification of SISD and SIMD processors. Vectorization of operations is built into the instruction repertoire of CodeAPeel, making it straightforward to simulate such processors with powerful vector instructions.