FPGA Implementations of Layered MinSum LDPC Decoders Using RCQ Message Passing

TL;DR

This paper presents FPGA implementations of layered MinSum LDPC decoders using RCQ message passing, demonstrating improved error correction and reduced hardware complexity with novel quantization methods.

Contribution

It introduces three FPGA design methods for RCQ message quantization in layered LDPC decoders and compares their performance and hardware efficiency to existing decoders.

Findings

4-bit L-msRCQ with Broadcast improves error correction by 0.03 dB.

3-bit L-msRCQ with Broadcast reduces hardware resources by 15-18%.

Trade-off between performance loss and hardware savings is demonstrated.

Abstract

Non-uniform message quantization techniques such as reconstruction-computation-quantization (RCQ) improve error-correction performance and decrease hardware complexity of low-density parity-check (LDPC) decoders that use a flooding schedule. Layered MinSum RCQ (L-msRCQ) enables message quantization to be utilized for layered decoders and irregular LDPC codes. We investigate field-programmable gate array (FPGA) implementations of L-msRCQ decoders. Three design methods for message quantization are presented, which we name the Lookup, Broadcast, and Dribble methods. The decoding performance and hardware complexity of these schemes are compared to a layered offset MinSum (OMS) decoder. Simulation results on a (16384, 8192) protograph-based raptor-like (PBRL) LDPC code show that a 4-bit L-msRCQ decoder using the Broadcast method can achieve a 0.03 dB improvement in error-correction performance while using 12% fewer registers than the OMS decoder. A Broadcast-based 3-bit L-msRCQ decoder uses 15% fewer lookup tables, 18% fewer registers, and 13% fewer routed nets than the OMS decoder, but results in a 0.09 dB loss in performance.