A survey on Dependable Digital Systems using FPGAs: Current Methods and Challenges

TL;DR

This survey reviews current fault tolerance methods for FPGA-based dependable digital systems, emphasizing their application in safety-critical domains and comparing various evaluation metrics.

Contribution

It provides a comprehensive overview of fault tolerance techniques for FPGAs, highlighting challenges and comparing evaluation metrics across different methods.

Findings

Fault tolerance techniques improve system reliability in safety-critical applications.

Hardware redundancy increases reliability but adds overhead.

Evaluation metrics vary significantly among different fault tolerance methods.

Abstract

Fault tolerance is increasingly being use to design Dependable Digital Systems (DDS), which refers to the capability of a system to keep performing its intended functions in existence of faults. DDS are typically used in Safety-critical system (SCS) such as medical (I&C) devices, Nuclear power Plants (I&C) devices and Aerospace (I&C) systems, the failure in these systems can cause harm to environment, death, injury to people. Different fault tolerance techniques were developed to overcome these issues and that has led to increase the reliability and dependability of applications on Field Programmable Gate Arrays (FPGAs). In this paper, multiple related works are present dealing with different types of faults and fault tolerance methods in FPGA based systems. Furthermore, a comparison between the evaluation metrics of previous works of Fault Tolerant (FT) techniques like hardware redundancy overhead, time delay, reliability, and performance are also present.