Demystifying Memory Access Patterns of FPGA-Based Graph Processing Accelerators

TL;DR

This paper evaluates FPGA-based graph processing accelerators using a simulation environment to compare their performance across different memory technologies and partitioning schemes, providing insights into their strengths and weaknesses.

Contribution

It introduces a simulation framework that enables fair comparison of existing FPGA-based graph accelerators across various configurations and memory technologies.

Findings

Memory technology impacts performance significantly.

Partitioning schemes influence efficiency and scalability.

The comparison reveals strengths and weaknesses of current accelerators.

Abstract

Recent advances in reprogrammable hardware (e.g., FPGAs) and memory technology (e.g., DDR4, HBM) promise to solve performance problems inherent to graph processing like irregular memory access patterns on traditional hardware (e.g., CPU). While several of these graph accelerators were proposed in recent years, it remains difficult to assess their performance and compare them on common graph workloads and accelerator platforms, due to few open source implementations and excessive implementation effort. In this work, we build on a simulation environment for graph processing accelerators, to make several existing accelerator approaches comparable. This allows us to study relevant performance dimensions such as partitioning schemes and memory technology, among others. The evaluation yields insights into the strengths and weaknesses of current graph processing accelerators along these dimensions, and features a novel in-depth comparison.