Error Floor Analysis of LDPC Row Layered Decoders

TL;DR

This paper develops a linear state-space model to analyze the error floor of QC LDPC codes with row layered decoding, revealing how layer order affects error performance and proposing methods to minimize the error floor.

Contribution

Introduces a novel state-space model incorporating layered scheduling effects and identifies layer order as a key factor in error floor reduction for LDPC decoders.

Findings

Layer order significantly impacts the error floor in layered LDPC decoding.

The proposed model accurately predicts error floor behavior.

Optimized layer ordering can substantially lower the error floor.

Abstract

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates.