iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform

TL;DR

This paper presents an FPGA-based architecture for real-time stereo matching using ELAS, significantly improving frame rate and energy efficiency over CPU implementations by optimizing modules and memory management.

Contribution

It introduces a hardware-friendly reformulation of ELAS's triangulation module and applies various optimizations to enable real-time, energy-efficient stereo matching on FPGA.

Findings

Achieves up to 38.4x frame rate improvement over CPU

Achieves up to 27.1x energy efficiency improvement

Enables real-time stereo matching on low-power FPGA platform

Abstract

Stereo matching is a critical task for robot navigation and autonomous vehicles, providing the depth estimation of surroundings. Among all stereo matching algorithms, Efficient Large-scale Stereo (ELAS) offers one of the best tradeoffs between efficiency and accuracy. However, due to the inherent iterative process and unpredictable memory access pattern, ELAS can only run at 1.5-3 fps on high-end CPUs and difficult to achieve real-time performance on low-power platforms. In this paper, we propose an energy-efficient architecture for real-time ELAS-based stereo matching on FPGA platform. Moreover, the original computational-intensive and irregular triangulation module is reformed in a regular manner with points interpolation, which is much more hardware-friendly. Optimizations, including memory management, parallelism, and pipelining, are further utilized to reduce memory footprint and improve throughput. Compared with Intel i7 CPU and the state-of-the-art CPU+FPGA implementation, our FPGA realization achieves up to 38.4x and 3.32x frame rate improvement, and up to 27.1x and 1.13x energy efficiency improvement, respectively.