Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications

TL;DR

This paper introduces fixed-posit, a simplified floating-point representation with fixed regime and exponent bits, offering significant power, area, and delay savings with minimal accuracy loss in error-resilient and neural network applications.

Contribution

It proposes fixed-posit as a new floating-point format with fixed parameters, and designs a fixed-posit multiplier demonstrating substantial efficiency improvements.

Findings

47% power savings over posit multipliers

Up to 70% power savings over IEEE-754 multipliers

Minimal accuracy loss in neural network applications

Abstract

Today, almost all computer systems use IEEE-754 floating point to represent real numbers. Recently, posit was proposed as an alternative to IEEE-754 floating point as it has better accuracy and a larger dynamic range. The configurable nature of posit, with varying number of regime and exponent bits, has acted as a deterrent to its adoption. To overcome this shortcoming, we propose fixed-posit representation where the number of regime and exponent bits are fixed, and present the design of a fixed-posit multiplier. We evaluate the fixed-posit multiplier on error-resilient applications of AxBench and OpenBLAS benchmarks as well as neural networks. The proposed fixed-posit multiplier has 47%, 38.5%, 22% savings for power, area and delay respectively when compared to posit multipliers and up to 70%, 66%, 26% savings in power, area and delay respectively when compared to 32-bit IEEE-754 multiplier. These savings are accompanied with minimal output quality loss (1.2% average relative error) across OpenBLAS and AxBench workloads. Further, for neural networks like ResNet-18 on ImageNet we observe a negligible accuracy loss (0.12%) on using the fixed-posit multiplier.