Algorithmic Obfuscation for LDPC Decoders

TL;DR

This paper introduces algorithmic obfuscation techniques for LDPC decoders that significantly impair their performance and security against attacks, with minimal area overhead, to protect intellectual property.

Contribution

It proposes two novel algorithmic-level obfuscation methods for LDPC decoders that degrade performance and resist attacks, a new approach in logic locking for error-correcting decoders.

Findings

Decoder throughput reduced to less than one-third

Error rate increased by over two orders of magnitude

Area overhead limited to 0.33%

Abstract

In order to protect intellectual property against untrusted foundry, many logic-locking schemes have been developed. The main idea of logic locking is to insert a key-controlled block into a circuit to make the circuit function incorrectly without right keys. However, in the case that the algorithm implemented by the circuit is naturally fault-tolerant or self-correcting, existing logic-locking schemes do not affect the system performance much even if wrong keys are used. One example is low-density parity-check (LDPC) error-correcting decoder, which has broad applications in digital communications and storage. This paper proposes two algorithmic-level obfuscation methods for LDPC decoders. By modifying the decoding process and locking the stopping criterion, our new designs substantially degrade the decoder throughput and/or error-correcting performance when the wrong key is used. Besides, our designs are also resistant to the SAT, AppSAT and removal attacks. For an example LDPC decoder, our proposed methods reduce the throughput to less than 1/3 and/or increase the decoder error rate by at least two orders of magnitude with only 0.33% area overhead.