Nanosecond machine learning event classification with boosted decision trees in FPGA for high energy physics

TL;DR

This paper introduces a highly low-latency FPGA implementation of boosted decision trees for real-time event classification in high energy physics, achieving 10 ns latency with minimal resource use.

Contribution

It presents a novel FPGA firmware implementation of BDTs with optimized layout and parameters, enabling ultra-fast classification suitable for trigger systems.

Findings

Latency of about 10 ns independent of clock speed

Low FPGA resource utilization (0.01% to 0.2%)

Effective in separating electrons vs. photons and Higgs vs. multijet processes

Abstract

We present a novel implementation of classification using the machine learning / artificial intelligence method called boosted decision trees (BDT) on field programmable gate arrays (FPGA). The firmware implementation of binary classification requiring 100 training trees with a maximum depth of 4 using four input variables gives a latency value of about 10 ns, independent of the clock speed from 100 to 320 MHz in our setup. The low timing values are achieved by restructuring the BDT layout and reconfiguring its parameters. The FPGA resource utilization is also kept low at a range from 0.01% to 0.2% in our setup. A software package called fwXmachina achieves this implementation. Our intended user is an expert of custom electronics-based trigger systems in high energy physics experiments or anyone that needs decisions at the lowest latency values for real-time event classification. Two problems from high energy physics are considered, in the separation of electrons vs. photons and in the selection of vector boson fusion-produced Higgs bosons vs. the rejection of the multijet processes.