Building Beyond HLS: Graph Analysis and Others

TL;DR

This paper examines the limitations of High-Level Synthesis (HLS) in FPGA programming, especially for complex data structures like graphs, and discusses potential improvements to make FPGA development more accessible.

Contribution

It identifies current shortcomings in HLS workflows for complex problems and proposes directions for higher-level tooling to enhance FPGA adoption for software developers.

Findings

HLS faces challenges with graph algorithms and complex control flows

Current HLS tools hinder FPGA adoption for non-expert programmers

Proposes higher-level tooling to address HLS limitations

Abstract

High-Level Synthesis has introduced reconfigurable logic to a new world -- that of software development. The newest wave of HLS tools has been successful, and the future looks bright. But is HLS the end-all-be-all to FPGA acceleration? Is it enough to allow non-experts to program FPGAs successfully, even when dealing with troublesome data structures and complex control flows -- such as those often encountered in graph algorithms? We take a look at the panorama of adoption of HLS by the software community, focusing on graph analysis in particular in order to generalise to \textit{FPGA-unfriendly} problems. We argue for the existence of shortcomings in current HLS development flows which hinder adoption, and present our perspective on the path forward, including how these issues may be remedied via higher-level tooling.