A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells
Ankit Wagle, Sunil Khatri, Sarma Vrudhula

TL;DR
This paper introduces TULIP, an energy-efficient ASIC architecture for binary neural networks that uses reconfigurable mixed-signal neurons, achieving three times the energy efficiency of conventional MAC-based designs.
Contribution
The paper presents a novel reconfigurable binary neuron implemented as a standard cell, along with algorithms for mapping BNNs onto a SIMD-based ASIC architecture, improving energy efficiency.
Findings
TULIP achieves 3x energy efficiency over conventional designs.
Reconfigurable binary neurons can implement all BNN operations.
No penalty in performance, area, or accuracy compared to traditional ASICs.
Abstract
This paper presents TULIP, a new architecture for a binary neural network (BNN) that uses an optimal schedule for executing the operations of an arbitrary BNN. It was constructed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a SIMD fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. The unique aspect of the binary neuron is that it is implemented as a mixed-signal circuit that natively performs the inner-product and thresholding operation of an artificial binary neuron. Moreover, the binary neuron, which is implemented as a single CMOS standard cell, is reconfigurable, and with a change in a single parameter, can implement all standard operations involved in a BNN. We present novel algorithms…
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