Optimal design of a superconducting transmon qubit with tapered wiring

TL;DR

This paper provides analytical formulas to predict surface dielectric loss in superconducting transmon qubits, highlighting the impact of wire tapering on reducing loss and offering insights into TLS spectrum characteristics.

Contribution

It introduces simplified analytical formulas for surface dielectric loss prediction and demonstrates how tapering wiring can significantly reduce qubit loss.

Findings

Tapering the wire reduces surface dielectric loss.

Formulas accurately predict loss based on geometry.

TLS spectrum size and density are predicted from surface dissipation sites.

Abstract

Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.