Exploration of Gate Trench Module for Vertical GaN devices

TL;DR

This paper investigates optimizing the gate trench module in vertical GaN devices by examining surface cleaning, dielectric thickness, and doping levels, leading to improved device performance and understanding of dielectric effects.

Contribution

It presents an experimental analysis of how surface cleaning, dielectric thickness, and doping influence the performance of vertical GaN devices, offering new insights into device optimization.

Findings

Good surface cleaning enhances device performance.

Gate dielectric thickness >35 nm narrows DC parameter distribution.

Lower p-doping improves ON-resistance.

Abstract

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.