A First Look at RISC-V Virtualization from an Embedded Systems Perspective

TL;DR

This paper presents the first public implementation and evaluation of the RISC-V hypervisor extension in embedded systems, demonstrating its feasibility and performance improvements through experiments on simulation and real hardware.

Contribution

It introduces a complete implementation of RISC-V H-extension v0.6.1, ported open-source hypervisor Bao, and extends platform-level interrupt and timer infrastructure for embedded systems.

Findings

Successful deployment on FireSim and Zynq UltraScale+ MPSoC

Low-latency, deterministic guest interrupt injection achieved

Open-sourced implementation supports RISC-V community efforts

Abstract

This article describes the first public implementation and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip core. To perform a meaningful evaluation for modern multi-core embedded and mixedcriticality systems, we have ported Bao, an open-source static partitioning hypervisor, to RISC-V. We have also extended the RISC-V platformlevel interrupt controller (PLIC) to enable direct guest interrupt injection with low and deterministic latency and we have enhanced the timer infrastructure to avoid trap and emulation overheads. Experiments were carried out in FireSim, a cycle-accurate, FPGA-accelerated simulator, and the system was also successfully deployed and tested in a Zynq UltraScale+ MPSoC ZCU104. Our hardware implementation was opensourced and is currently in use by the RISC-V community towards the ratification of the H-extension specification.