Sparse Deconvolution Methods for Online Energy Estimation in Calorimeters Operating in High Luminosity Conditions

TL;DR

This paper introduces sparse deconvolution algorithms for online energy estimation in calorimeters, demonstrating that they improve accuracy over standard methods and are feasible for FPGA implementation despite higher computational costs.

Contribution

It proposes novel sparse representation-based iterative deconvolution methods optimized for online processing in high luminosity calorimeters.

Findings

Sparse deconvolution methods outperform standard techniques in energy estimation accuracy.

The Separable Surrogate Functional is feasible for FPGA implementation in real-time systems.

Proposed methods balance computational cost and performance for online applications.

Abstract

Energy reconstruction in calorimeters operating in high luminosity particle colliders has become a remarkable challenge. In this scenario, pulses from a calorimeter front-end output overlap each other (pile-up effect), compromising the energy estimation procedure when no preprocessing for signal disentanglement is accomplished. Recently, methods based on signal deconvolution have been proposed for both online and offline reconstructions. For online processing, constraints concerning fast processing, memory requirements, and cost implementation limit the overall performance. Offline reconstruction allows the use of Sparse Representation theory to implement sophisticated Iterative Deconvolution methods. This paper presents Iterative Deconvolution methods based on Sparse Representation algorithms whose computational cost is effective for online implementation. Using simulated data, current techniques were compared to the proposed Sparse Representation ones for performance validation in the online environments. Analysis has shown that, despite the higher computational cost, when compared to standard methods, the performance improvement may justify the use of the proposed techniques, in particular for the Separable Surrogate Functional, which is shown to be feasible for implementation in modern FPGAs.