Reducing Redundancy in Data Organization and Arithmetic Calculation for Stencil Computations

TL;DR

This paper introduces a novel transpose layout and temporal computation folding techniques to reduce data redundancy and reorganization overhead in stencil computations, improving performance on modern CPUs.

Contribution

It proposes a new transpose layout for better data locality and a temporal computation folding approach to minimize arithmetic redundancy in stencil computations.

Findings

Achieves improved data locality and reduced reorganization overhead.

Effectively exploits register reuse to lower arithmetic redundancy.

Demonstrates competitive performance on AVX-2 and AVX-512 CPUs.

Abstract

Stencil computation is one of the most important kernels in various scientific and engineering applications. A variety of work has focused on vectorization techniques, aiming at exploiting the in-core data parallelism. Briefly, they either incur data alignment conflicts or hurt the data locality when integrated with tiling. In this paper, a novel transpose layout is devised to preserve the data locality for tiling in the data space and reduce the data reorganization overhead for vectorization simultaneously. We then propose an approach of temporal computation folding designed to further reduce the redundancy of arithmetic calculations by exploiting the register reuse, alleviating the increased register pressure, and deducing generalization with a linear regression model. Experimental results on the AVX-2 and AVX-512 CPUs show that our approach obtains a competitive performance.