An Efficient Vectorization Scheme for Stencil Computation

TL;DR

This paper introduces a novel transpose layout and a time loop unroll-and-jam strategy to enhance vectorization and data locality in stencil computations, achieving improved performance on modern CPUs.

Contribution

A new transpose layout combined with a time loop unroll-and-jam technique that addresses data alignment and locality issues in stencil vectorization.

Findings

Achieves competitive performance on AVX-2 and AVX-512 CPUs.

Reduces data reorganization overhead in vectorized stencil computation.

Improves data reuse at register level through multistep computation.

Abstract

Stencil computation is one of the most important kernels in various scientific and engineering applications. A variety of work has focused on vectorization and tiling techniques, aiming at exploiting the in-core data parallelism and data locality respectively. In this paper, the downsides of existing vectorization schemes are analyzed. Briefly, they either incur data alignment conflicts or hurt the data locality when integrated with tiling. Then we propose a novel transpose layout to preserve the data locality for tiling and reduce the data reorganization overhead for vectorization simultaneously. To further improve the data reuse at the register level, a time loop unroll-and-jam strategy is designed to perform multistep stencil computation along the time dimension. Experimental results on the AVX-2 and AVX-512 CPUs show that our approach obtains a competitive performance.