The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing

TL;DR

This paper details the second-generation SpiNNaker chip's processing element architecture, featuring adaptive biasing, dynamic scaling, accelerators for neural network computations, and a dedicated network-on-chip, enabling efficient hybrid neuromorphic processing.

Contribution

It introduces a new PE architecture with advanced features like adaptive biasing, accelerators, and a system-level design centered around an ARM M4 core for hybrid neural network processing.

Findings

Successful implementation of the PE architecture in 22nm FDSOI.

Benchmarks demonstrate effective operation on SNN, DNN, and hybrid networks.

Enhanced processing speed and efficiency for neuromorphic computing tasks.

Abstract

This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level, processing is centered around an ARM M4 core, similar to the processor-centric architecture of the first generation SpiNNaker. To speed operation of subtasks, we have added accelerators for numerical operations of both spiking (SNN) and rate based (deep) neural networks (DNN). PEs communicate via a dedicated, custom-designed network-on-chip. We present three benchmarks showing operation of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.