Quantifying the Efficacy of Logic Locking Methods

TL;DR

This paper introduces two metrics to evaluate the effectiveness of logic locking methods in protecting integrated circuit designs against intellectual property theft, providing a standardized way to compare different techniques.

Contribution

It proposes new metrics and a flow for approximating them, enabling better assessment of logic locking techniques' efficacy against various attack scenarios.

Findings

Metrics effectively differentiate locking techniques

Flow approximates metrics on generic circuits

Evaluation reveals varying resistance levels among methods

Abstract

The outsourced manufacturing of integrated circuits has increased the risk of intellectual property theft. In response, logic locking techniques have been developed for protecting designs by adding programmable elements to the circuit. These techniques differ significantly in both overhead and resistance to various attacks, leaving designers unable to discern their efficacy. To overcome this critical impediment for the adoption of logic locking, we propose two metrics, key corruption and minimum corruption, that capture the goals of locking under different attack scenarios. We develop a flow for approximating these metrics on generic locked circuits and evaluate several locking techniques.