On the Performance of Dual-Gate Reconfigurable Nanowire Transistors

TL;DR

This paper examines dual-gate reconfigurable nanowire transistors, comparing configurations at drain and source, revealing trade-offs in switching behavior and non-linear output characteristics based on fabrication and biasing conditions.

Contribution

It introduces dual-gate silicon nanowire FETs with specific fabrication techniques and analyzes their operation in different configurations, highlighting the impact on switching and output behavior.

Findings

PGAD configuration suppresses ambipolar operation but worsens switching due to Schottky barriers.

PGAS configuration achieves MOSFET-like switching but exhibits non-linear output at small bias.

Fabrication yields Schottky junctions influencing device performance.

Abstract

We investigate the operation of dual-gate reconfigurable field-effect transistor (RFET) in the programgate at drain (PGAD) and program-gate at source (PGAS) configurations. To this end, dual-gate silicon nanowire (SiNW) FETs are fabricated based on anisotropic wet chemical silicon etching and nickel silicidation yielding silicide-SiNW Schottky junctions at source and drain. Whereas in PGAD-configuration ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky-barrier. Operating the RFET in PGAS configuration yields a switching behavior close to a conventional MOSFET. This, howewer, needs to be traded off against strongly non-linear output characteristics for small bias.