GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent

TL;DR

GradPIM introduces a practical processing-in-DRAM architecture that accelerates deep neural network training by enhancing memory bandwidth and performance with minimal protocol and area overhead.

Contribution

It proposes a simple, incremental PIM architecture extending DDR4 SDRAM to improve DNN training efficiency without protocol invasion.

Findings

Significant performance improvement in DNN training.

Substantial reduction in memory bandwidth usage.

Minimal overhead to memory protocol and DRAM area.

Abstract

In this paper, we present GradPIM, a processing-in-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.